The Effects of ESR and ESL in Digital Decoupling Applications Written By: Jeffrey Cain, Ph.D Abstract: It is common place for digital integrated circuits to operate at switching frequencies of 100 MHz and above, even at the circuit board level. As these frequencies continue to increase, the parasitic of the decoupling capacitors must be considered. A study on the effects of equivalent series resistance (ESR) and equivalent series inductance (ESL) in a typical digital decoupling application is presented. Utilizing SPICE, it can be shown that the ESR and ESL of chip capacitors can dramatically alter the voltage seen by the integrated circuit (IC). By changing the values of the parasitics and comparing the results to the ideal case for a
Decoupling / Low Inductance
So Many Electrons, So Little Time… The Need for Low Inductance Capacitors Written By: John Galvagni | Sara Randall | Paul Roughan | Allen Templeton Abstract: High di/dt ratios, large current pulses over short times, are an inevitable part of today’s fast electronic circuitry. They can cause high voltage spikes when passing through paths that have inductance. The task of the designer then, is to have high energies available, but not the associated voltage excursions, by reducing the total inductance. Eliminating wire bonds, reducing path lengths, and using low inductance components is the regimen. This paper describes the availability of capacitors that can go a long way to providing the energies needed, but simultaneously, lower the intrinsic inductance it contributes.
PE Series Capacitors Decoupling and/or Filtering Written By: John D. Prymak Abstract: Decoupling is a means of eliminating or reducing those elements which restrict high speed operations. Filtering is driven by two considerations – emission and susceptance. The noise generated in high speed digital operations may need to be reduced, to achieve accepted levels of emission to prevent interference with other systems. Also, the system itself may have its distinct level of noise tolerance which would require filtering selected inputs to maintain integrity of the logic circuit operations. The solution to a decoupling problem may assist filtering, and vice versa; but, the optimum solution to either is not the optimum solution for the other. The PE devices were originally designed
Low Inductance Capacitors For Digital Circuits Written By: John Galvagni Abstract: Ceramic capacitors have become one of the limiting factors in digital circuits because of intrinsic characteristics such as equivalent series resistance and inductance. There are many things which could be done to mitigate that, and we describe some of those in this paper. AVX’s DCAP capacitor, (developed with and for IBM) is used as a benchmark to show how much can be done to improve the situation. We compare and contrast that part to those currently available.
LICA® Design Guide Written By: Phil Troup Abstract: A review of high frequency decoupling basics highlighting the advantages of using LICA® with its C4 terminations in these applications.
Land Grid Array (LGA) Low Inductance Capacitor Advantages in Military and Aerospace Applications Written By: Sonja Brown Abstract: The benefits of Land Grid Array (LGA) capacitors and superior low inductance performance in modern military and aerospace designs.
Introduction to Choosing MLC Capacitors For Bypass/Decoupling Applications Written By: Yun Chase Abstract: Methods to ensure signal integrity using decoupling capacitors have been the topic of many papers in the past as well as in the present. One can find equally many methods of decoupling as well. This paper will illustrate one of these established methods and introduce it in a theoretical sense using the most simplistic of terms. The paper will also describe the methods of the past (in slow speed systems) and the practices of the present (in high speed systems).
Interconnect Schemes for Low Inductance Ceramic Capacitors Written By: Jeff Cain, Ph.D. Abstract: As digital electronic systems continue to operate at higher and higher frequencies, the use of low inductance decoupling capacitors continues to increase. The parasitic inductance of the devices themselves is important, but the method used to connect the components to the system, such as printed circuit boards (PCB), is also a considerable factor. Adding inductance in the connection scheme can eliminate some of the effectiveness of the use of these low inductance elements. This paper will examine some of the different schemes utilized at the board level to minimize the loop inductance of the decoupling capacitors.
Inductance Measurements for Multi-Terminal Devices Written By: Ben Smith Abstract: New innovations in both the telecommunication industry as well as the computer industry have mandated a need for using low inductance capacitive devices in power supply decoupling applications. With this being the case, different concepts for the construction of these devices have recently been the key to the success of reaching inductances of less than 50pH. There is, however, a significant bottleneck to the new innovation process due to measurement techniques. Most of the newer devices are using techniques such as multi-path current flow, short length, and equal and opposite current injection techniques to achieve low inductance levels. Also, coupled with these new designs is the need for higher energy
Improved Noise Suppression via Multilayer Ceramic Capacitors (MLCs) in Power-Entry Decoupling Written By: Arch Martin | R. Kenneth Keenan Abstract: A new decoupling technique is proposed for surface mounted designs that recommends using 0.1 µF MLCs as the circuit-level decoupling capacitors and 1.0 µF to 10 µF MLCs in place of the tantalum as the board-level power-entry capacitor. This combination of MLCs on each PCB coupled with a single system level tantalum or aluminum is probably an optimum arrangement; performance is enhanced, and cost is not increased.